Test and Reliability of Nano-Electronic Systems

The RealTest Project is a joint project of the Universities of Freiburg (Bernd Becker, Ilia Polian), Stuttgart (Hans-Joachim Wunderlich), and Paderborn (Sybille Hellebrand), and the Fraunhofer Institute of Integrated System Design and Design Automation Dresden (Bernd Straube, Wolfgang Vermeiren). It is funded by the German National Science Foundation (Deutsche Forschungsgemeinschaft / DFG) and focuses on quality assurance and reliability of nano-electronic systems. Industrial partners are Infineon Technologies, Neubiberg, and Mentor Graphics, Hamburg.

The project targets integrated systems in nanoscale CMOS technologies. Nanoscale manufacturing processes are characterized by an increasing vulnerability to defects and by increasing parameter variations both among and inside chips. The "International Technology Roadmap for Semiconductors" expects that by 2019 feature sizes of 7 nm will be reached, and with current design stategies yields would go down to 20% or even 10%. Furthermore systems will become more susceptible to transient fault during system operation.

Consequently, a robust design will become mandatory, which in turn results in completely new challenges in testing.  As systems are designed to compensate faults to a certain extent, test quality is no longer directly related to fault coverage. Instead information about the remaining robustness in the presence of faults is needed. Within the framework of the RealTest Project unified design and test strategies will be developed supporting both a robust design and efficient strategies for manufacturing test as well as online test and fault tolerance. The project partners focus on the following topics:

Fault Modeling for Digital Components in Nanoscale CMOS (Dresden)

The decreasing feature sizes of future technologies result in defects and parameter variabilities which cannot be accurately characterized by existing fault models. New fault models will be developed comprising, in particular, statistical profiles of circuit parameters and conditions for fault detection. 

Modeling, Verification, and Test of Acceptable Behavior (Freiburg)

The behavior of nanoscale systems may be "acceptable" within a certain range, which is possibly application specific (e.g. accuracy or speed). Metrics for "acceptable behavior" will be developed taking into account aspects of both offline and online testing. Based on this, new strategies and algorithms for automatic test pattern generation (ATPG) will be investigated and combined with the ATPG techniques for fault tolerant systems developed in Paderborn.

Testing Fault Tolerant Nanoscale Systems (Paderborn)

On the one hand robust design styles are contradictory to traditional design for testability rules, as they decrease the observability of faults. On the other hand fault masking helps to increase yield. Consequently a paradigm shift in testing is needed. A "go/nogo" test result is no longer satisfactory, instead information about the remaining robustness in the presence of faults is needed. To support such a "quality binning" metrics will be developed and integrated into ATPG algorithms.

State Monitoring in Complex Systems (Stuttgart)

While online testing and monotoring of memory arrays is already state of art, respective techniques for logic circuitry are still in their infancy. As the percentage of flipflops in logic components is rapidly growing and flipflops are particularly susceptible to hard and soft errors, quality assurance for memory elements in logic components is of major importance. Within the framework of the project monitoring techniques and reconfiguration strategies will be developed uniquely applicable to both manufacturing and online test. In particular new and robust hardware structures for scan chains will be developed.