Language:
A. Czutro, M. E. Imhof, J. Jiang, A. Mumtaz, M. Sauer, B. Becker, I. Polian and H.-J. Wunderlich, "Variation-Aware Fault Grading," to appear in Proc. 21st IEEE Asian Test Symposium (ATS12), Niigata, Japan, November 19-22, 2012.
M. Sauer, A. Czutro, I. Polian and B. Becker, "Small-Delay-Fault ATPG with Waveform Accuracy," IEEE International Conference on Computer Aided Design (ICCAD12), San Jose, California, USA, November 5-8, 2012.
L. Feiten, M. Sauer, T. Schubert, A. Czutro, E. Böhl, I. Polian and B. Becker, "#SAT-based Vulnerability Analysis of Security Components — A Case Study," IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systemse (DFT12), Austin, Texas, USA, October 3-5, 2012.
A. Cook, S. Hellebrand, H.-J. Wunderlich, "Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test," 17th IEEE European Test Symposium (ETS12), Annecy, France, May 28-June 1, 2012.
S. Hillebrecht, M. Kochte, H.-J. Wunderlich, B. Becker, "Exact Stuck-at Fault Classification in Presence of Unknowns," 17th IEEE European Test Symposium (ETS12), Annecy, France, May 28-June 1, 2012.
D.A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, M.E. Imhof, H.-J. Wunderlich, "A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures," 30th IEEE VLSI Test Symposium (VTS12), Hawaii, USA, April 23-26 2012.
A. Czutro, M. Sauer, T. Schubert, I. Polian and B. Becker, "SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms," 30th IEEE VLSI Test Symposium (VTS12), Hawaii, USA, April 23-26, 2012.
A. Cook, S. Hellebrand, M.E. Imhof, A. Mumtaz, H.-J. Wunderlich, "Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test," Proc. 13th IEEE Latin-American Test Workshop (LATW12), Quito, Ecuador, April 10-13, 2012.
J. Jiang, M. Sauer, A. Czutro, B. Becker and I. Polian, "On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints," Conference on Design, Automation and Test in Europe (DATE12), Grenoble, France, March 18-22, 2012.
M. Sauer, S. Kupferschmid, A. Czutro, S. M. Reddy and B. Becker, "Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation," accepted for 25th International Conference on VLSI Design, Hyderabad, India, January 7-11, 2012.
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, "Diagnostic Test of Robust Circuits," accepted for Proceedings IEEE 20th Asian Test Symposium (ATS11), New Delhi, India, November 21- 23, 2011.
A. Mumtaz, M. E. Imhof, S. Holst, H.-J. Wunderlich, "Embedded Test for Highly Accurate Defect Localization," accepted for Proceedings IEEE 20th Asian Test Symposium (ATS11), New Delhi, India, November 21-23, 2011.
M. Sauer, J. Jiang, A. Czutro, I. Polian and B. Becker, "Efficient SAT-Based Search for Longest Sensitisable Paths," accepted for Proceedings IEEE 20th Asian Test Symposium (ATS11), Neu Delhi, India, November 21-23, 2011.
M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian, B. Becker, "SAT-based analysis of sensitisable paths," 14th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2006.
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, "Robuster Selbsttest mit Diagnose," 5. GMM/GI/ITG Fachtagung Zuverlässigkeit und Entwurf (ZuE11), Hamburg, Germany, September 27-29, 2011. [VDE]
A. Mumtaz, M. E. Imhof, S. Holst, H.-J. Wunderlich, "Eingebetteter Test zur hochgenauen Defekt-Lokalisierung," 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE11), Hamburg, Germany, September 27-29, 2011. [VDE]
M. E. Imhof, H.-J. Wunderlich, "Korrektur transienter Fehler in eingebetteten Speicherelementen," 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE11), Hamburg, Germany, September 27-29, 2011. [VDE]
M. E. Imhof, H.-J. Wunderlich, "Soft Error Correction in Embedded Storage Elements," Proceedings IEEE International On-Line Testing Symposium (IOLTS11), Athens, Greece, July 13-15, 2011. [IEEE]
M. Sauer, A. Czutro, I. Polian, B. Becker, "Estimation of Component Criticality in Early Design Steps," Proceedings IEEE International On-Line Testing Symposium (IOLTS11), Athen, Greece, July 13-15, 2011. [IEEE]
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W.Vermeiren, H.-J. Wunderlich, "Variation-Aware Fault Modeling," IEEE 19th Asian Test Symposium (ATS), Shanghai, China, December 1-4, 2010. [IEEE]
M. Gulbins, F. Hopsch, P. Schneider, B. Straube and W. Vermeiren, "Developing Digital Test Sequences for Through-Silicon Vias within 3D Structures," IEEE International 3D System Integration Conference, Munich, Germany, November 16-18, 2010. [IEEE]
T. Indlekofer, M. Schnittger, S. Hellebrand, "Efficient Test Response Compaction for Robust BIST Using Parity Sequences," Proceedings 28th IEEE International Conference on Computer Design (ICCD'10), Amsterdam, Netherlands, October 2010. [IEEE]
T. Indlekofer, M. Schnittger, S. Hellebrand, "Robuster Selbsttest mit extremer Kompaktierung," Proceedings 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Wildbad Kreuth, Germany, September 2010. [VDE]
F. Hopsch, B. Straube, and W. Vermeiren. "Ermitteln der Häufigkeitsverteilungen von Verzögerungszeiten digitaler Grundgatter infolge von Parameterschwankungen," Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS), Dresden, Germany, May 18-19, 2010, pp. 19-25. [Fraunhofer]
V. Froese, R. Ibers, S. Hellebrand, "Reusing NoC-infrastructure for test data compression," 28th VLSI Test Symposium (VTS), Santa Cruz, CA, USA, April 19-22, 2010. [IEEE]
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, "Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung," Proceedings 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, Stuttgart, Germany, September, 2009. [VDE]
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, "ATPG-Based Grading of Strong Fault-Secureness," Proceedings 15th IEEE International On-Line Testing Symposium (IOLTS'09), Sesimbra-Lisbon, Portugal, June 2009. [IEEE]
I. Polian, S. M. Reddy, I. Pomeranz, X. Tang, and B. Becker, "On reducing circuit malfunctions caused by soft errors," Proceedings IEEE International Symposium on Defect and Fault Tolerance, Cambridge, MA, USA, November 2008. (Poster). [IEEE]
M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin, "Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung," Tagungsband der 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'08), Ingolstadt, Germany, 29.September - 1.October 2008. [VDE]
M. Hunger, S. Hellebrand, "Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG," Tagungsband der 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'08), Ingolstadt, Germany, 29.September - 1.October 2008. [VDE]
M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin, "Integrating Scan Design and Soft Error Correction in Lowpower Applications," Proceedings 14th IEEE International On-Line Testing Symposium (IOLTS'08), Rhodes, Greece, July 7-9, 2008, pp. 59-64. [IEEE]
M. Hunger and S. Hellebrand, "Verification and Analysis of Self-Checking Properties through ATPG," Proceedings 14th IEEE International On-Line Testing Symposium, Rhodes, Greece, July 7-9, 2008, pp. 25-30. [IEEE]
C. G. Zoellin, H.-J. Wunderlich, I. Polian, B. Becker, "Selective Hardening in Early Design Steps," Proceedings 13th IEEE European Test Symposium (ETS'08), Lago Maggiore, Italy, May 25-29, 2008, pp. 185-190. [IEEE]
U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, "Signature Rollback - A Technique for Testing Robust Circuits," Proceedings IEEE VLSI Test Symposium, San Diego, CA, USA, April 27 - May 1, 2008, pp. 125-130. [IEEE]
I. Polian, S. M. Reddy, and B. Becker, "Scalable calculation of logical masking effects for selective hardening against soft errors," Proceedings International Symposium on VLSI, Montpellier, April 2008, pp. 257-262. [IEEE]
T. Coym, M. Claus, "Implementation of DC-Fault Diagnosis Networks in Standard Circuit Simulators," ANALOG’08, 10. GMM/ITG-Fachtagung, Siegen, Germany, April 2008. [VDE]
M. Versen, J. Kneževic, S. M. Montoya, T. Coym, W. Vermeiren und B. Straube, "Fehleranalyse für DRAM Teilschaltungen durch Extraktion von Layout Parasitics," ANALOG’08, 10. GMM/ITG-Fachtagung, Siegen, Germany, April 2008. [VDE]
M. A. Kochte, C. G. Zoellin, M. E. Imhof, H.-J. Wunderlich, "Test Set Stripping Limiting the Maximum Number of Specified Bits," Proceedings 4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008, pp. 581-586 (Best Paper Award). [IEEE]
S. Hellebrand, Christian G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, "A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction," Proceedings International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 2007, pp. 50-58. [IEEE]
I. Polian, D. Nowroth, and B. Becker, "Identification of critical errors in imaging applications," Proceedings International On-Line Test Symposium, Heraklion, Greece, July 2007, pp. 201-202 (Poster). [IEEE]
M. E. Imhof, C. G. Zoellin, H.-J. Wunderlich, "Scan Test Planning for Power Reduction," Proceedings 44th ACM/IEEE Design Automation Conference (DAC'07), San Diego, CA, USA, June 4-8, 2007, pp. 521-526. [IEEE]
J. P. Hayes, I. Polian, and B. Becker, "An analysis framework for transient-error tolerance," Proceedings IEEE VLSI Test Symposium, Berkeley, CA, USA, 2007, pp. 249-255. [IEEE]
M. E. Imhof, C. G. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra, "Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute," Tagungsband der GMM/GI/ITGFachtagung Zuverlässigkeit und Entwurf (ZuD'07), Munich, Germany, 26. - 28. March 2007, pp. 69- 76. [VDE]
I. Polian, J. P. Hayes, D. Nowroth, and B. Becker, "Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate," Proceedings GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuD'07), Munich, Germany, 26-28 March 2007, pp. 183-184 (Poster). [VDE]
M. Versen, J. Kneževic, S. M. Montoya, W. Vermeiren, T. Coym, and B. Straube, "A Defect Oriented Circuit Simulation Approach Applied to D-RAM Designs," 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, Munich, Germany, March 2007, pp. 177-178. [VDE]
I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara, "Low-cost hardening of image processing applications against soft errors," Proceedings International Symposium on Defect and Fault Tolerance, Arlington, VA, USA, 2006, pp. 274-279. [IEEE]
M. Claus, T. Coym, A. Reibiger, and B. Straube, "Kennlinienmethode zur DC-Fehlerdiagnose integrierter Analogschaltungen," 9. ITG/GMM-Fachtagung Entwicklung von Analogschaltungen mit CAE Methoden (Analog’06), Dresden, Germany, September 2006. [VDE]
M. Freibothe, J. Döge, T. Coym, S. Ludwig, B. Straube und E. Kock, "Verification-Oriented Behavioral Modeling of Non-Linear Analog Parts of Mixed-Signal Circuits," Forum on Specification & Design Languages FDL’06, Darmstadt, Germany, September 2006. [Fraunhofer]
S. Kundu and I. Polian, "An improved technique for reducing false alarms due to soft errors," Proceedings International On-Line Test Symposium, Como, Italy, July 2006, pp. 105-110. [IEEE]
R. Kothe, H. T. Vierhaus, T. Coym, W. Vermeiren, and B. Straube, "Embedded Self Repair by Transistor and Gate Level Reconfiguration – Possibilities and Limitations," 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS06), Prague, Czech Republic, April 2006 (best paper award). [IEEE]
B. Becker, S. Hellebrand, I. Polian, B. Straube, W.Vermeiren, H.-J.
Wunderlich,
"Massive Statistical Process Variations - A Grand Challenge for
Testing Nanoelectronic Circuits," 4th Workshop on Dependable and Secure
Nanocomputing (WDSN10), Chicago, IL, USA, June 28 - July 01, 2010, pp.
95-100.
S. Hellebrand, Christian G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, "Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance," Informacije MIDEM, Vol. 37, No. 4(124), Ljubljana, Slovenia, December 2007, pp. 212-219.
S. Hellebrand, Christian G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, "Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance," Proceedings MIDEM 2007 - International Conference on Microelectronics, Devices and Materials and the Workshop on Electronic Testing, Bled, Slovenia, September 2007, pp. 3-10.
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, "Test und Zuverlässigkeit nanoelektronischer Systeme," Tagungsband der GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuD'07), Munich, Germany, 26. -28. March 2007, pp. 139-140.
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, "DFG Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project RealTest - Test and Reliability of Nano- Electronic Systems)," it - Information Technology, Vol. 48, No. 5, 2006, pp. 304-311.
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, "Adaptive Test and Diagnosis of Intermittent Faults," Latin American Test Workshop (LATW13), Cordoba, Argentina, April 2013
A. Cook, S. Hellebrand, H.-J. Wunderlich, "Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern," 24. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'12), Cottbus, Germany, February 2012
J. Jiang and M. Sauer and A. Czutro and B. Becker and I. Polian, "On the Optimality of K Longest Path Generation," IEEE Workshop on RTL and High Level Testing (WRTLT), Jaipur, India, 2011.
M. Gulbins, F. Hopsch, P. Schneider, B. Straube and W. Vermeiren, "Applying Electric Fault Simulation for Deriving Tests for Through-Silicon Vias," IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), November 2010.
F. Hopsch, B. Straube, W. Vermeiren, M. Lindig, and J. Haase. "Elektrische Fehlersimulation digitaler Grundgatter unter Parameterschwankungen : Methodik und erste Ergebnisse," GI/ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Paderborn, Germany, February 28th - March 2nd, 2010.
V. Froese, R. Ibers, S. Hellebrand, "Testdatenkompression mit Hilfe der Netzwerkinfrastruktur," GI/ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Paderborn, Germany, 28. February 28th - March 2nd, 2010.
I. Polian, S. M. Reddy, I. Pomeranz, X. Tang, and B. Becker, "No free lunch in soft error protection?," Workshop on Dependable and Secure Nanocomputing , Anchorage, AK, USA, 2008.
M.E. Imhof, H.-J. Wunderlich, C.G. Zoellin, "Integrating Scan Design and Soft Error Correction in Low- Power Applications," 1st Workshop on Low Power Design Impact on Test and Reliability (LPonTR08), Verbania, Italy, May 25-29, 2008.
M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin, J. Leenstra, N. Maeding, "Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information," GI/ITG/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen," Vienna, Austria, February 2008.
T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. Zöllin, "Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Strahlungsempfindlichkeit," GI/ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Vienna, Austria, February 2008 (Poster).
I. Polian, J. P. Hayes and B. Becker, "Cost-efficient circuit hardening based on critical soft error rate," IEEE Workshop on RTL ATPG and DfT, Beijing, China, 2007.
B. Straube, W. Vermeiren, M. Lindig, T. Coym, L. Grobelny, and A. Lerch, "Fault Diagnosis of Analog Integrated Circuits Using an Analog Fault Simulator," 12th Int. Mixed-Signal Testing Workshop, Edinburgh, UK, June, 2006.
M. Claus, T. Coym, A. Reibiger, and B. Straube, "A Network Theoretical Approach to Analog DC-Fault Diagnosis," 12th Int. Mixed-Signal Testing Workshop, Edinburgh, UK, June, 2006.
I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara, "Period of grace: A new paradigm for efficient soft error hardening," GI/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Freiburg, Germany, 2006.
J. P. Hayes, I. Polian, and B. Becker, "A model for transient faults in logic circuits," IEEE International Design and Test Workshop, Dubai, UAE, Jan 2006.
F. Hopsch, H.-J. Wunderlich, I. Polian, B. Becker and S. Hellebrand, "Special Panel Session: Testing Nanoelectronic Circuits Under Massive Statistical Process Variations," IEEE 20th Asian Test Symposium (ATS11), New Delhi, India, November 21- 23, 2011.
S. Hellebrand, H.-J. Wunderlich, Panel: "Collaborative Test Research in Europe," 13th IEEE European Test Symposium (ETS'08), Verbania, Italy, May 25-29, 2008.
B. Becker, S. Hellebrand, B. Straube, H.-J. Wunderlich, Panel: "Test, Diagnose und Zuverlässigkeit in zukünftigen elektronischen Systemen," ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'06), Titisee, Germany, March 12-14, 2008.
"Defect-Tolerance, Error-Tolerance: Which way to go? How?," IEEE Workshop on RTL ATPG and DfT, Beijing, CN, 2007.
"Error-tolerance: Are good-enough chips good-enough?," IEEE European Test Symposium, Freiburg, Germany, 2007.
H.-J. Wunderlich, "Challenges in Test and Diagnosis - or: Complexity is more than Size," Colloque National 2008, Groupement de Recherche, System-On-Chip et System-In-Package, Paris, June 13-15, 2008.
S. Hellebrand, "Reliable Nanoscale Systems – Challenges and Strategies for On- and Offline Testing," Invited Talk at IEEE East-West Design & Test Symposium (EWDTS’07), Yerevan, Armenia, September 2007.
"Resource-constrained error handling in digital circuits," Intel Santa Clara, USA, May 2007 (Host: Dr. Abhijit Jas).
"Test, verfication and validation of products," Endress & Hauser Flowtec, Reinach, Switzerland, May 2007 (Host: Dr. Ulrich Kaiser).
"Transient-error tolerance," Nara Institute of Science and Technology (NAIST), Nara, Japan, November 2006 (Host: Prof. Hideo Fujiwara).
"Transient-error tolerance," Yale University, New Haven, USA, October 2006 (Host: Prof. Yiorgos Makris).
I. Polian, "Soft errors in micro and nanoelectronics," Embedded Tutorial, GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'07), Munich, Germany, 26-28 March 2007